The present invention relates generally to a method of fabricating sub-lithographic sized line and space patterns. More specifically, the present invention relates to a method of fabricating sub-lithographic sized line and space patterns on various substrates using a combination of conventional microelectronics processes including photolithographic patterning and etching, polysilicon etching, polysilicon oxidation, and polysilicon deposition.
Nano-imprinting lithography is a promising technique for obtaining nano-size patterns (as small as a few tens of nanometers). A key step in forming the nano-size patterns is to first form an imprinting stamp that includes a pattern that complements the nano-sized patterns. Typically, the imprinting stamp includes sub-lithographic sized line and space patterns that are carried by a substrate material. The imprinting stamp is urged into contact with another substrate that includes a mask layer. The mask layer can be a polymer such as a photoresist material, for example. The sub-lithographic sized line and space patterns are transferred to the mask layer and are replicated therein. Typically, subsequent microelectronics processing steps are used to transfer the sub-lithographic patterns from the mask layer to an underlying layer positioned below the mask layer.
A standard method in the microelectronics industry for patterning features on a substrate uses well understood photolithographic processes. Typically, a layer of photoresist is coated onto a substrate material followed by exposing the photoresist with a light source through a mask. The mask includes patterned features, such as lines and spaces, that are to be transferred to the photoresist. After the photoresist is exposed, the photoresist is etched or is immersed in a solvent to define the patterns that were transferred to the photoresist. The patterns produced by this process are typically limited to line widths greater than a lithography limit xcex of a photolithographic alignment tool, which is ultimately limited by a wavelength of light of a light source used to expose the photoresist. At present, a state of the art photolithographic alignment tool is capable of printing line widths as small as xcex=100.0 nm.
Features patterned into the photoresist are transferred into the substrate material using well known microelectronics processes such as ion milling, plasma etching, or chemical etching, for example. Using standard microelectronics processing methods, lines or spaces with a feature size (i.e. a width) greater than or equal to xcex or a grating (a line-space sequence) with a period greater than or equal to 2xcex can be created.
However, in many applications it is advantageous to have features such as lines and spaces be as small as possible. Smaller line widths or periods translate into higher performance and/or higher density circuits. Hence, the microelectronics industry is on a continual quest to reduce the minimum resolution in photolithography systems and thereby reduce the line widths or periods on patterned substrates. The increases in performance and/or density can be of considerable economic advantage because the electronics industry is driven by a demand for faster and smaller electronic devices. The imprinting stamps used for nano-imprinting lithography are just one example of an application in which it is necessary to have line and space patterns that are as small as possible and that have a feature size that is less than the lithography limit xcex.
Consequently, there exists a need for method of fabricating sub-lithographic sized line and space patterns that utilizes conventional microelectronics processes including conventional lithography systems to fabricate the sub-lithographic sized line and space patterns with a feature size that is less than the lithography limit xcex of the lithography system.
The method of fabricating sub-lithographic sized line and space patterns of the present invention address the need for fabricating sub-lithographic sized line and space patterns using conventional microelectronics processes.
A plurality of sub-lithographic line and space patterns that can be used for applications including but not limited to an imprinting stamp in a nano-imprinting lithography process, micro-electro-mechanical systems, and sub-lithographic optical systems can be fabricated using conventional microelectronics processes including photolithographic patterning and etching, polysilicon deposition, polysilicon oxidation, polysilicon oxide etching, polysilicon wet and plasma etching, and chemical mechanical planarization.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.